The present invention relates to a semiconductor memory device, and more particularly, to a technique for reducing a fabrication cost by shortening a test time of a parallel test of a semiconductor memory device.
Development of a process technology is leading to high integration of a semiconductor memory device. To ensure chip reliability, the semiconductor memory device is tested with expensive test equipment over a long period of time after its fabrication.
In a device test technique, it is important to achieve a high-speed of a test performed on tens of millions of cells, as well as reliability of the test. Particularly, since a fabrication cost is directly affected by a development time of a semiconductor memory device and a test time until product release, shortening the test time is considered very important in fabrication efficiency and competition between manufacturers.
In general, a cell-by-cell test increases the cost and test time in determining a cell pass/fail of a memory chip for a highly integrated semiconductor memory device.
Therefore, a parallel test mode is used to reduce the test time.
In a parallel test, identical data are written into a plurality of cells, and then an exclusive OR logic gate is used for a read operation to determine a pass with ‘1’ when the identical data are read from the plurality of cells, and determine a fail with ‘0’ when different data are read even from one cell. Accordingly, the test time can be reduced.
FIG. 1 illustrates a process of a conventional parallel test performed on a semiconductor memory device having eight memory banks by using four data pins. In this drawing, as well as in FIG. 2, ACT=activate, WT=write, RD=read and PCG=pre-charge.
In a write operation of the conventional parallel test, banks 0 to 3 are simultaneously activated, and identical data are simultaneously written into the activated banks 0 to 3. Thereafter, banks 4 to 7 are simultaneously activated, and identical data are also written into the banks 4 to 7, simultaneously.
Like the write operation, in a read operation of the conventional parallel test, the banks 0 to 3 are simultaneously activated, and the data are simultaneously read out from the activated banks 0 to 3 and compressed. Then, a result of pass/fail is output to a data pin (DQ). Thereafter, the banks 4 to 7 are simultaneously activated, and the data are simultaneously read out from the activated banks 4 to 7 and compressed. Then, a result of pass/fail is output to a data pin (DQ).
In the general parallel test, when N banks are simultaneously tested, data of the respective banks are simultaneously output, and compressed results are output using N data pins (DQ) representing the N banks, respectively. For example, a result of data compression of the bank 0 is output to a data pin 0 (DQ0), and a result of data compression of the bank 1 is output to a data pin 1 (DQ1).
Thus, if the parallel test is performed on a memory device having eight memory banks with only four data channels allocated from test equipment, the banks are divided into halves and a write/read operation is performed twice as shown in FIG. 1. Since all the banks are not simultaneously tested and the write/read operation is performed twice, the test time of the memory device increases.
Of course, the read/write operation may be performed simultaneously on all the banks by allocating eight data channels from the test equipment. However, as more data channels are allocated from the test equipment, the test equipment simultaneously tests less chips. This also increases the test time.
Alternatively, a method of increasing a compression ratio may be employed in the parallel test. For example, by increasing the compression ratio, data of the banks 0 and 1 may be compressed together and output to the data pin 0 (DQ0), and data of the banks 2 and 3 may be compressed together and output to the data pin 1 (DQ1). If this method is used, the parallel test can be simultaneously performed on the eight banks with only four data channels allocated. However, the increased compression ratio in the parallel test degrades efficiency of Y repair.
This is because in the case where the data of the banks 0 and 1 are compressed together and output to the data pin 0 (DQ0), both banks 0 and 1 must be examined to find a defective data cell when a signal indicating a ‘fail’ is output to the data pin 0 (DQ0), whereas in the case where data of only the bank 0 is compressed and output to the data pin 0 (DQ0), only the bank 0 is examined to find a defective data cell.
Also, since the test equipment is limited in applicable amount of current, a defective operation may be caused because of a voltage drop, which is a phenomenon where a voltage supplied from the test equipment drops, if the write/read operation is performed simultaneously on all the banks of the memory device.